Hsiuping University of Science and Technology Institutional Repository : Item 310993100/1237

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HUSTIR > College of Engineering > Department of Electrical Engineering & Graduate Institute > Journal > Item 310993100/1237

Please use this identifier to cite or link to this item: http://ir.hust.edu.tw/dspace/handle/310993100/1237

Title:	Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters
Authors:	C. Y. Wu;M. C. Shiau
Date:	1990-10
Issue Date:	2009-02-03T06:46:46Z
Relation:	IEEE J. Solid-State Circuits, pp. 1247-1256
Appears in Collections:	[Department of Electrical Engineering & Graduate Institute] Journal

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