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http://ir.hust.edu.tw/dspace/handle/310993100/2248
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| 題名: | 具單一位元線與低待機必v消耗之靜態隨機存取記憶體
SRAM with single bit line and low standby power consumption |
| 作者: | 廖笙緯 |
| 貢獻者: | 電機工程研究所 |
| 關鍵詞: | SRAM
負載電晶體
驅動電晶體
存取電晶體
待機模式 |
| 日期: | 2009-07
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| 上傳時間: | 2011-05-23T05:52:25Z
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| 摘要: | 在修平研究所這兩年說短不短說長不長，指導教授蕭明椿老師不只教導我在學術上的研究，平時就對待任何事情，也時常提醒我態度的謹慎，將所做事情完善的處理好。除了蕭老師之外也受到很多老師的關懷，不管在研究所的課程還是未來出社會找工作都一直有提出一些看法與我們探討，所長更是為了我們的研究環境想盡辦法，使我們能夠專心學習。
This thesis presents two kinds of novel single/dual SRAM with single bit line and low standby power consumption, one kind is SRAM having a lower source terminal voltage of PMOS load transistors in writing operation and another kind is SRAM having a higher voltage word-line in writing operation.
Firstly a lower source terminal voltage of PMOS load transistors in writing operation can lead to higher equivalent resistance of NMOS driving transistor during the write-logic-1 access, where logic-0 is originally stored. Therefore, a higher divided voltage between NMOS access transistor and NMOS driving transistor can be obtained. As a result, the difficulty of write-logic-1 operation can be resolved. Secondly a higher voltage word-line in writing operation can lead to lower equivalent resistance of NMOS access transistor during the write-logic-1 access, where logic-0 is originally stored. Therefore, a higher divided voltage between NMOS access transistor and NMOS driving transistor can also be obtained. As a result, the difficulty of write-logic-1 operation can be remedied.
The less standby power consumption in this thesis is by way of reduction of potential difference between source terminal voltage of PMOS load transistor and source terminal voltage of NMOS driving transistor.
In this thesis, two kinds of novel single/dual SRAM can not only resolve the difficulty of write-logic-1 operation but also lessen standby power consumption as verified by HSPICE results. |
| 描述: | 指導教授：蕭明椿博士 |
| 顯示於類別: | [電機工程系(含碩士班)] 學位論文
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