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Title: 具高阻抗之靜態隨機存取記憶體
Authors: 魏芃葦;陳翊綸
Contributors: 電機工程系
Keywords: 高阻抗 SARM 靜態隨機記憶體 HSPICE
Date: 2011-12-07
Issue Date: 2012-07-25T06:04:19Z
Abstract: 本專題所提出之具高靜態雜訊邊際及低待機功率消耗之SRAM,其經使用TSMC 90奈米CMOS製程參數加以模擬,證實其不但可有效避免寫入邏輯1困難之問題,並能有效降低待機功率,且具良好的靜態雜訊邊際(SNM),再者,即使將電源供應電壓下降至1.0V特,並使用TSMC 90奈米CMOS製程參數加以模擬,仍能具有良好的性能
Appears in Collections:[Department of Electrical Engineering & Graduate Institute] Monograph

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