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HUSTIR > College of Engineering > Department of Electrical Engineering & Graduate Institute > Theses and Dissertations > Item 310993100/3866

Please use this identifier to cite or link to this item: http://ir.hust.edu.tw/dspace/handle/310993100/3866

Title:	應用於低功率低電壓之高性能雙邊緣觸發正反器 A High Performance Dual Edge-Triggered Flip-Flop for Low-Power Low-Voltage Applications
Authors:	陳冠廷
Contributors:	電機工程研究所
Keywords:	高性能低功率雙邊緣觸發正反器移位暫存器具電位轉換之雙邊緣觸發正反器
Date:	2011-06
Issue Date:	2013-11-19T08:49:31Z
Abstract:	本論文提出一種適合應用於低功率低電壓之高性能雙邊緣觸發正反器電路設計。在低功率及低電壓之VLSI電路設計中，雙邊緣觸發正反器的使用已廣泛的受到重視。單邊緣觸發正反器(Single Edge-Triggered Flip-Flop; SETFF)每個週期內只使用了兩個邊緣中的一個，第二個邊緣則被浪費了。雙邊緣觸發正反器(Dual Edge-Triggered Flip-Flop; DETFF)使用了時脈信號的上升和下降邊緣。在相同的時脈頻率條件下，雙邊緣觸發正反器能夠提供兩倍於單邊緣觸發正反器的資料傳輸速率。本論文將與八篇先前所提出之雙邊緣觸發正反器電路針對電晶體數量、性能、功率損耗以及在不同工作電壓和不同工作頻率下的結果分析與比較。本論文係使用TSMC 180nm的製程技術去模擬分析與比較。根據模擬結果顯示，本論文所提出之雙邊緣觸發正反器能有效減少功率損耗達53.8%，並能改善功率延遲乘積(Power Delay Product; PDP)和能量延遲乘積(Energy Delay Product; EDP)達70%及83.1%。此外，本論文將這些雙邊緣觸發正反器電路應用於一傳統的移位暫存器架構，於同一測試環境下，比較在不同工作電壓下的功率損耗分析。根據模擬結果，本論文所提出之雙邊緣觸發正反器具有最低的功率損耗，並能工作於較低的工作電壓。最後，本論文將所提出之雙邊緣正反器電路應用於一具有電位轉換功能之正反器電路，並與兩篇先前所發表的電路做比較。 In the research of low-power and low-voltage VLSI circuits design, the use of dual edge-triggered flip-flop (DETFF) has gained more attention. This thesis describes a novel dual edge-triggered flip-flop circuit design for low-power low-voltage applications. Single edge-triggered flip-flops (SETFFs) use only one of the two clock edges per cycle. The second edge is wasted. However, the dual edge-triggered flip-flops (DETFFs) use both clock edges and can provide a data rate that is twice that of single edge-triggered flip-flops for the same clock frequency. In this thesis, we compare eight previously published dual edge-triggered flip-flops with our proposed design for their transistor counts, performance, power dissipation, and low-voltage low-power applications at different voltage and frequency. HSPICE simulation results employing TSMC 180nm CMOS technology indicate the proposed flip-flop can reduce effectively power dissipation up to 53.8% as compared to other DETFFs. Moreover, the improvements in power-delay product and energy-delay product are enhanced up to 70% and 83.1% individually at different lower supply voltages. In addition, we apply to a classic shift register using these DET flip-flops and compare their power dissipation at different power supply voltages. Simulation results indicate that the proposed flip-flop has the lowest power dissipation. Finally, we apply the proposed circuit to a level converting dual edge-triggered flip-flop and compare with two previously published circuits to verify the feasibility.
Description:	指導教授:余建政
Appears in Collections:	[Department of Electrical Engineering & Graduate Institute] Theses and Dissertations

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