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HUSTIR > College of Engineering > Department of Electrical Engineering & Graduate Institute > Theses and Dissertations > Item 310993100/3873

Please use this identifier to cite or link to this item: http://ir.hust.edu.tw/dspace/handle/310993100/3873

Title:	具高靜態雜訊邊際及低待機功率消耗之靜態隨機存取記憶體 SRAM with high static noide margin and low standby power consumption
Authors:	張恩誌
Contributors:	電機工程研究所
Keywords:	待機啟動電路待機模式背閘極漏電流靜態雜訊邊際
Date:	2011-06
Issue Date:	2013-11-20T08:26:23Z
Abstract:	本研究提出一種新穎架構之具高靜態雜訊邊際及低待機功率消耗之SRAM，其主要包括一記憶體陣列、複數個控制電路以及一待機啟動電路，而記憶體陣列是由複數列記憶晶胞與複數行記憶晶胞所組成，每一列記憶晶胞設置一個控制電路、待機啟動電路、抗雜訊邊際啟動電路，且每一記憶晶胞由一寫入用選擇電晶體M3、二NMOS 驅動電晶體M1和M2、二PMOS負載電晶體P1和P2、二NMOS讀取用電晶體M4和M5、二控制反相器PC1和MC1以及PC2和MC2所組成。每一控制單元係連接至對應列記憶晶胞中之每一記憶晶胞的二NMOS 驅動電晶體的源極端，以便因應不同操作模式而控制該等源極電壓，於寫入模式時，將選定晶胞中較接近寫入用位元線WBL之驅動電晶體M1的源極電壓VL1設定成較接地電壓為高之一第一預定電壓且將選定晶胞中另一驅動電晶體M2的源極電壓VL2設定成接地電壓，以便防止寫入邏輯1困難之問題；於待機模式時，將所有記憶晶胞中之驅動電晶體的源極電壓設定成較接地電壓為高之一第二預定電壓，以便降低漏電流；而於其他模式時則將記憶晶胞中之驅動電晶體的源極電壓設定成接地電壓，以便維持讀取穩定度。再者，將每一記憶體晶胞中之該驅動電晶體M1的背閘極(back gate)連接至該由PC1和MC1所組成控制反相器之輸出端，以及將該驅動電晶體M2與該寫入用選擇電晶體M3的背閘極均該連接至該由PC2和MC2所組成控制反相器之輸出端，以便有效提高雙埠靜態隨機存取記憶體之靜態雜訊邊際（SNM)。另外，藉由該待機啟動電路的設計，可有效促使靜態隨機存取記憶體快速進入待機模式，並因而大幅提高靜態隨機存取記憶體之待機效能。本研究所提出之具高靜態雜訊邊際及低待機功率消耗之SRAM，其經使用TSMC 90奈米CMOS製程參數加以模擬，證實其不但可有效避免寫入邏輯1困難之問題，並能有效降低待機功率，且具良好的靜態雜訊邊際（SNM），再者，即使將電源供應電壓下降至1.0V特，並使用TSMC 90奈米CMOS製程參數加以模擬，仍能具有良好的性能。 This paper describes a new circuit approach for a Static Random Access Memory （SRAM）with high Static Noide Margin（SNM） and low standby power consumption comprising a memory array, a plurality of control units and a standby start-up circuit. The memory array comprises a plurality of rows of memory cells and a plurality of columns of memory cells. Each row of memory cells consists of a control unit, and each memory cell consists of a NMOS write selection transistor M3, two NMOS driver transistors M1 and M2, two PMOS load transistors P1 and P2, two NMOS read selection transistors M4 and M5, as well as two control inverters using PC1 with MC1 and PC2 with MC2. The key point is that the control unit is connected to the sources of the said NMOS driver transistors in each row. The control unit controls the source voltages of the said NMOS driver transistors for resolving the difficulty of write-logic-1 operation and for reducing leakage current of memory cells. In a write mode, the source voltage of near bit-line driver transistor is equal to a first preset voltage larger than a ground voltage and another driver transistor is the ground voltage to solve the write-logic-1 problem. In a stand-by mode, the source voltages of the said NMOS driver transistors are equal to a second preset voltage larger than a ground voltage to reduce leakage current. In other modes, the source voltages of the said NMOS driver transistors are the ground voltage to maintain read stability. Moreover, the back gate of driver transistor M1 is connected to output of the control inverter PC1 and MC1, and both the back gate of driver transistor M2 and the back gate of write selection transistor M3 are connected to output of the control inverter PC2 and MC2 , therefore the SNM can be improved. Furthermore, the standby start-up circuit can speed up the proposed SRAM with improved SNM and low standby power consumption reaching a standby condition. Based upon the verifications employing TSMC 90nm CMOS process, the proposed SRAM with improved SNM and low standby power consumption can resolve the difficulty of write-logic-1 operation and they also come with advantages like less standby power as well as good SNM. In addition, the proposed SRAM with improved SNM and low standby power consumption can be applied to guarantee acceptable results even a supply voltage below 1.0V while employing TSMC 90nm CMOS process.
Description:	指導教授:蕭明椿
Appears in Collections:	[Department of Electrical Engineering & Graduate Institute] Theses and Dissertations

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