Hsiuping University of Science and Technology Institutional Repository : Item 310993100/601

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HUSTIR > College of Engineering > Department of Electrical Engineering & Graduate Institute > Patents > Item 310993100/601

Please use this identifier to cite or link to this item: http://ir.hust.edu.tw/dspace/handle/310993100/601

Title:	可降低讀取干擾之三電晶體式DRAM晶胞 A DRAM OF A 3-TRANSISTOR CELL WITH REDUCED READ DISTURBANCE
Authors:	蕭明椿
Contributors:	修平技術學院
Date:	2005-09-21
Issue Date:	2008-11-06T08:23:53Z
Abstract:	本創作提出一種可降低讀取干擾之三電晶體式DRAM晶胞，其係由一寫入電晶體N1、一儲存電晶體N2以及一讀取電晶體N3所組成，其中，該寫入電晶體N1和該儲存電晶體N2係為NMOS電晶體，而該讀取電晶體N3係為PMOS電晶體，並且將該儲存電晶體N2之源極由先前技藝連接至接地端，變更為連接至讀取字元線(RW)，該讀取字元線(RW)於讀取操作期間係設定為接地電壓，而於讀取操作以外之期間則設定為電源電壓。藉此，即可阻斷非選擇(nonselected)DRAM晶胞之漏電流(leaking current)，並達成有效降低讀取干擾及有效提高讀取可靠度之功效。
Appears in Collections:	[Department of Electrical Engineering & Graduate Institute] Patents

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