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HUSTIR > College of Engineering > Department of Electrical Engineering & Graduate Institute > Monograph > Item 310993100/4071

Please use this identifier to cite or link to this item: http://ir.hust.edu.tw/dspace/handle/310993100/4071

Title:	5T 單埠靜態隨機存取記憶體改良
Authors:	陳冠廷;王璿睿
Contributors:	本校出版品
Keywords:	記憶體改良
Date:	2013
Issue Date:	2014-07-16T06:44:03Z
Abstract:	傳統6T 靜態隨機存取記憶體（SRAM）晶胞由於需要6 顆電晶體，需設置互補位元線，且驅動電晶體與存取電晶體間的電流驅動能力比（即單元比率cell ratio）通常需設定在2.2 至3.5 之間[1]，而導致存在有高集積化困難及價格高等缺失。用來減少6T SRAM 晶胞之電晶體數之一種方式為具單一位元線之5T SRAM 晶胞，迄今，有許多具單一位元線之SRAM 晶胞之技術[2]-[7]被提出。其中，如下圖1.1（a）所示，M. Ukita 等人[2]所提出具SCPA（Single-bit-line Cross-Point cell Activation）結構之SRAM 晶胞雖可減少地區解碼器（local decoder）之數量，惟須設置二個呈串聯連接並用以分別接收行位址與列位址之存取電晶體
Appears in Collections:	[Department of Electrical Engineering & Graduate Institute] Monograph

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BD99A01-具低讀取功率消耗之5T靜態隨機存取記憶體之設計-實務專題書面.pdf	1197Kb	Adobe PDF	2038	View/Open