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http://ir.hust.edu.tw/dspace/handle/310993100/215
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| 題名: | A Power-Saving CMOS Level Converter for Dual Supply Voltages |
| 作者: | Chien-Cheng Yu |
| 貢獻者: | Department of Electrical Engineering |
| 關鍵詞: | Power saving
Level converter
contention |
| 日期: | 2001-09
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| 上傳時間: | 2008-08-19T07:40:55Z
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| 摘要: | When using dual supply voltages, the circuit requires level converters at the interface of V(DDH) and V(DDL) gates to block the static current which occurs if a V(DDH) gate drives a V@@ gate. In this paper, a Power-Saving level converter (PSLC) is proposed which has the advantages of low power consumption and high operating speed, and it may operate at different values of V@ ranging from 1.2V to 4.2V. These level converters are simulated for different capacitive loads and operating supply voltage levels using the HSPICE parameters of a 0.35 fim digital CMOS technology. HSPICE simulation results show that an average power saving of 50% and 60% speed increase can be obtained compared to those of the existing technique.Hence, the proposed technique is suited for low power design without degrading performance. |
| 關聯: | 修平學報 3, 101-110 |
| 顯示於類別: | [電機工程系(含碩士班)] 期刊論文
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文件中的檔案:
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| 03-07使用於雙供應電壓之低功率位準轉換器設計.pdf | 490Kb | Adobe PDF | 1428 | 檢視/開啟 |
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